DocumentCode
1627286
Title
Developing a fast and inexpensive low power design strategy
Author
Singh, Mandeep ; Giacomotto, Christophe ; Oklobdzija, Vojin G.
Author_Institution
Univ. of California Davis, Dallas, TX
fYear
2008
Firstpage
1
Lastpage
4
Abstract
A low power circuit design strategy is presented. We believe this methodology can be used to develop fast and inexpensive techniques to aid designers in power optimizations which are generally compute time hungry. The design strategy explored allows for fast sizing of the circuit to get to within 5% of an optimal operating point in terms of energy. Traditional optimization for energy uses time consuming, exhaustive simulations to determine the best possible operating point. The design rules being developed aim to predict the energy optimal point with accuracy but more importantly assist designers to arrive at a minimum energy solution quickly and explore design options better. Furthermore these rules can be used to develop optimization tools which are several orders of magnitude faster than current linear programming and convex optimization tools.
Keywords
logic circuits; logic design; logic gates; low-power electronics; convex optimization tools; linear programming; logic gates; low power circuit design; Capacitance; Circuit simulation; Circuit synthesis; Computational modeling; Delay; Design optimization; Digital circuits; Guidelines; Minimization; Visualization;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems Workshop: System-on-Chip - Design, Applications, Integration, and Software, 2008 IEEE Dallas
Conference_Location
Dallas, TX
Print_ISBN
978-1-4244-2955-4
Electronic_ISBN
978-1-4244-2956-1
Type
conf
DOI
10.1109/DCAS.2008.4695925
Filename
4695925
Link To Document