A testable realization of CMOS combinational circuits

The KR realization (see S. Kundu and S.M. Reddy, Proc. 18th Int. Fault-Tolerant Computing Symp., p.220-25 1988) was proposed with the aim of designing testable CMOS combinational circuits using only primitive gates and no extraneous hardware. It is shown that for some useful Boolean functions the size of the KR realization is exponential in the number of input variables. The author presents a testable realization of a CMOS combinational circuit, with respect to FET (field-effect-transistor) stuck-open faults, named FM-CMOS. It uses only two-input multiplexers and, to an extent, addresses the size-problem of the KR realization. More specifically, it is shown that for some useful Boolean functions for which the size of the KR realization is exponential in the number of input variables the size of the FM-CMOS realization is polynomial in the number of input variables. For this reason, it is proposed that the FM-CMOS realization be used in conjunction with the KR realization. The results are applied to design a testable n-b CMOS adder that uses only O(n) FETs