Minimizing matching network loss in output harmonic matched power amplifiers using harmonic load-pull measurement

This paper proposes a harmonic matching network with minimum loss based on precise harmonic load pull measurement to enhance the efficiency and gain for harmonic matched power amplifiers. In this method, the number of stubs for harmonic matching network was reduced in order to minimize the loss and increase the efficiency. A power amplifier with a GaN transistor at 2.45 GHz frequency was designed to test and validate the approach. The fabricated power amplifier showed an improvement of around 0.2 dB in the loss of the output matching network, which corresponds to an improvement of more than 3% in the power amplifier efficiency compared to a conventional harmonic matching network. This new matching topology allowed reaching 72.9% drain efficiency and 14.46 dB gain.