A low-error statistical fixed-width multiplier and its applications

In this paper, an error compensation method for fixed-width two´s-complement multipliers is proposed. According to the statistical analysis for the truncation term, a general form for different word length compensation circuit is made up. For example, the proposed 8×8 fixed-width multiplier achieves 15.65% accuracy compared with direct-truncation multiplier. Also, the proposed multiplier has 41% savings compared with post-truncation multiplier when it is implemented in a 0.18-μm process. As the proposed multipliers applying to discrete cosine transform (DCT) design to demonstrate the system performance, the results show the proposed core can save 15% area with 9.2 dB peak signal-to-noise ratio (PSNR) penalty. Therefore, the proposed multiplier has a low hardware cost achieving high accuracy designs.