CRC circuit design for SRAM-Based FPGA configuration bit correction

Field Programmable Gate Arrays (FPGAs) are used in a variety of applications. However, the SRAM-based FPGAs can be easily influenced by single event upset (SEU) in the configuration memory. SEU could lead to a series of catastrophic consequence ranging from unwanted functional, data loss, or failure of the whole systems. So it´s very important to find a way to mitigating the SEU effect. In this paper, the existing techniques for SEU mitigation are introduced, and their shortcomings are pointed out. A new mitigation algorithm is proposed. Experimental results indicate that our algorithm is both feasible and effective.