• DocumentCode
    1630579
  • Title

    A built-in self-repair scheme for NOR-type flash memory

  • Author

    Hsiao, Yu-Ying ; Chen, Chao-Hsun ; Wu, Cheng-Wen

  • Author_Institution
    Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu
  • fYear
    2006
  • Lastpage
    119
  • Abstract
    The strong demand of non-volatile memory for SOC and SIP applications has made flash memory increasingly important. However, deep submicron defects and process uncertainties are causing yield loss of memory products. To solve the yield issue, built-in self-repair (BISR) is widely believed to be cost effective. It is, however, non-trivial to implement BISR on flash memories. In this paper we propose a BISR scheme for NOR-type flash memory. The BISR scheme performs built-in self-test (BIST), built-in redundancy analysis (BIRA), as well as on-chip repair. A typical redundancy architecture for NOR-type flash memory is assumed, based on which we present a redundancy analysis (RA) algorithm. Experimental result shows that the proposed BISR scheme can effectively repair most defective memories
  • Keywords
    built-in self test; flash memories; logic circuits; system-in-package; system-on-chip; NOR; SIP; SOC; built-in redundancy analysis; built-in self-repair; built-in self-test; flash memories; Algorithm design and analysis; Built-in self-test; Circuit faults; Flash memory; Nonvolatile memory; Performance analysis; Performance evaluation; Random access memory; Redundancy; Testing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Test Symposium, 2006. Proceedings. 24th IEEE
  • Conference_Location
    Berkeley, CA
  • Print_ISBN
    0-7695-2514-8
  • Type

    conf

  • DOI
    10.1109/VTS.2006.5
  • Filename
    1617572