DocumentCode
163108
Title
Processor yield at 14nm and beyond
Author
Yeric, Greg
Author_Institution
R&D, ARM Austin, Austin, TX, USA
fYear
2014
fDate
24-27 March 2014
Firstpage
111
Lastpage
116
Abstract
This paper discusses process integration and yield issues in advanced technology nodes and examines the related concerns and opportunities in the test structure field.
Keywords
integrated circuit testing; microprocessor chips; advanced technology nodes; process integration; processor yield; size 14 nm; test structure field; Delays; FinFETs; Layout; Logic gates; Market research; Metals;
fLanguage
English
Publisher
ieee
Conference_Titel
Microelectronic Test Structures (ICMTS), 2014 International Conference on
Conference_Location
Udine
ISSN
1071-9032
Print_ISBN
978-1-4799-2193-5
Type
conf
DOI
10.1109/ICMTS.2014.6841477
Filename
6841477
Link To Document