Trigger voltage walk-in effect of ESD protection device in HVCMOS

Author

Miao, Meng ; Dong, Shurong ; Li, Mingliang ; Han, Yan ; Song, Bo ; Ma, Fei

Author_Institution

Dept. of Inf. Sci. & Electron. Eng., Zhejiang Univ., Hangzhou, China

fYear

2010

Firstpage

1627

Lastpage

1629

Abstract

Transmission Line Pulse (TLP) curve of high voltage SCR-LDMOS (SCR embedded in LDMOS) is measured under various repetitious TLP stress to evaluate its Electrostatic Discharge (ESD) protection capability. Results show that trigger voltage has walk-in behavior. TCAD simulation indicates its mechanism involved is explained by a base push-out effect dominated melt filament growth, that turns a robust ESD clamp into a fragile device susceptible to trigger voltage collapse.

Keywords

CMOS integrated circuits; circuit simulation; electrostatic discharge; power semiconductor devices; technology CAD (electronics); thyristors; transmission lines; trigger circuits; ESD protection device; HVCMOS; TCAD simulation; TLP curve; base push-out effect; electrostatic discharge protection; high voltage SCR-LDMOS; melt filament growth; transmission line pulse; trigger voltage collapse; trigger voltage walk-in effect; Electrostatic discharge; Impact ionization; Resistance; Robustness; Stress; Thyristors; ESD; SCR-LDMOS; Trigger Voltage Walk-in;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State and Integrated Circuit Technology (ICSICT), 2010 10th IEEE International Conference on

Conference_Location

Shanghai

Print_ISBN

978-1-4244-5797-7

Type

conf

DOI

10.1109/ICSICT.2010.5667417

Filename

5667417