Reconfigurable resource architecture improves VLSI tester utilization

A VLSI tester which can be reconfigured from one high pin count test head to multiple independent lower pin count test heads is described. This reconfigurable resource architecture is shown to provide improved tester utilization for the factory. Greater utilization results in reduced capital equipment costs, thus reducing test costs for the test equipment user. A reconfigurable resource architecture also provides greater flexibility for future upgrades as a result of changing pin count combinations or increased pin count