DocumentCode
1631570
Title
Multi-cycle sensitizable transition delay faults
Author
Abraham, Jais ; Goel, Uday ; Kumar, Arun
Author_Institution
Texas Instruments (India) Pvt. Ltd., Bangalore
fYear
2006
Lastpage
313
Abstract
Transition fault testing has been traditionally performed on full scan sequential circuits using a two vector test; the first vector is used to initialize a node while the second vector is used to sensitize the fault on the node and to propagate the fault effects to an observation point. Although a two pattern test is good for detecting most of the delay faults that can cause circuits to malfunction, there are certain delay defects that cannot be detected using this test generation approach. In this paper, we review this class of delay faults which require three or more vectors for their detection. We show how launch-off-shift (LOS) transition fault patterns can be used effectively to detect some of these faults thus improving the quality of the delay fault tests. We also explore methods to minimize the yield loss incurred on account of using LOS patterns
Keywords
delays; sequential circuits; delay faults; full scan sequential circuits; launch-off-shift transition fault patterns; transition fault testing; two vector test; Circuit faults; Circuit testing; Clocks; Delay effects; Electrical fault detection; Fault detection; Instruments; Performance evaluation; Sequential analysis; Sequential circuits;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Test Symposium, 2006. Proceedings. 24th IEEE
Conference_Location
Berkeley, CA
Print_ISBN
0-7695-2514-8
Type
conf
DOI
10.1109/VTS.2006.49
Filename
1617609
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