A digit-serial compiler operator library

Author

Hartley, Richard ; Corbett, Peter

Author_Institution

Gen. Electr. Res. & Dev. Center, Schenectady, NY, USA

fYear

1989

Firstpage

641

Abstract

The PARSIFAL compiler is conceived for higher-throughput applications, allowing chips to be designed with throughput sample rates of up to 30 MHz, containing 300-400 MOPS on a chip of moderate size (250-mil²). Details are presented of the library of digit-serial cells used to implement arithmetic operations on digit-serial data. A description is given of the design of digit-serial addition/subtraction, multiplication, and shifting cells, and it is indicated how division can be carried out. The multiple precision and staggered-digit data formats are described. These formats allow greater precision and higher throughput to be achieved when needed

Keywords

circuit CAD; digital arithmetic; logic CAD; microprocessor chips; program compilers; 30 MHz; CAD; PARSIFAL compiler; addition; compiler operator library; digit-serial cells; division; higher-throughput applications; multiple precision data formats; multiplication; processor chip design; shifting cells; staggered-digit data formats; subtraction; Arithmetic; Chip scale packaging; Circuits; Clocks; Concurrent computing; Data flow computing; Libraries; Research and development; Silicon compiler; Throughput;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1989., IEEE International Symposium on

Conference_Location

Portland, OR

Type

conf

DOI

10.1109/ISCAS.1989.100433

Filename

100433