A novel low-power adiabatic SRAM with an energy-efficient line driver

A novel 64×64 bit adiabatic SRAM is designed using 0.25 μm CMOS technology. An adiabatic line driver, which does not have non-adiabatic loss on output loads through using feedback control from the next-stage buffer, is used to recover the charge of the large switching capacitance on the bit-lines and word-lines in a fully adiabatic manner. The power consumption of the proposed SRAM is significantly reduced because the energy transferred to the large capacitance buses is mostly recovered. The energy and functional simulations are performed using the net-list extracted from the layout. HSPICE simulation results indicate energy savings of 75% to 85%, as compared to the conventional CMOS implementation, for clock rates ranging from 25 to 200 MHz.