Semiconductor manufacturing: future process challenges

Summary form only given. Current advanced generation semiconductor integrated circuits incorporate photolithographic features of 0.5 microns and contain up to five separate wiring levels. This presentation will concentrate on new process technology requirements which must be achieved to advance technology to smaller devices, higher density, lower power consumption, and higher operating speed. Operating voltages are anticipated to decrease from 3.3 volts to 0.5 to 1.0 volts by the end of the century-primarily driven by the need to reduce power dissipation as more and faster circuits are incorporated onto each chip. Some of the changes will involve improving substrate crystalline defect and chemical contamination levels, reducing etch dimension variation due to spacial variations in the process equipment and the patterns being etched, adoption of chemical mechanical polish techniques to provide planar surfaces for use with 0.25 micron lithography patterns, and ultra clean clustered process equipment to permit lower cost manufacturing techniques to be realized