One New In-Operation Self-Testability Mechanism Designed for SoC Microchips following IEEE STD 1500

Because of changing temperature, silicon´s wearing out, and the other unpredictable factors, besides testing on chips when leaving factory, in some applications, such like life-protected and aviation system, microchips need real-time and in-operation test even if they have been used in system. This paper focuses on a new in-operation self-testing mechanism. This mechanism is used to detect the silicon defects of cores of SoC chips in working state. It makes embedded cores to automatically check their failures by themselves based on IEEE std I500TM and Core Test Language. According to Experiments, as a compromise, this In-operation Self-Test mechanism slows down the computation performance of SoC chips. Using this mechanism ensures finding exception in time and in turn adopting spare scheme in time, as well as it outperforms previous approaches in reducing cost of importing failure tolerance mechanisms into SoC chips.