On the way to heterogeneous nanoelectronics, towards the zero power and zero variability world

Nanoelectronics will have to face major challenges in the next decades in order to proceed with increasing progress to the sub 10 nm nodes: approach zero variability, reduce leakage currents and access resistances at the same time, fully exploit 3D integration at the device, elementary function, chip and system levels. New progress laws combined to the scaling down of CMOS based technology will emerge to enable new paths to Functional Diversification. New materials and disruptive architectures, mixing logic and memories, Heterogeneous Integration, introducing 3D schemes at the Front End and Back End levels, will come into play to make it possible.