A 0.13-μm, 0.78-μm2 low-power four-transistor SRAM cell with a vertically stacked poly-silicon MOS and a dual-word-voltage scheme

We developed a four-transistor SRAM cell with a vertically stacked poly-silicon MOS. Its size-fabricated by using 0.13-μm technology - is 0.78 μm², that is, only 38% of that of a six-transistor SRAM cell. By optimizing the threshold voltages and the gate-oxide thicknesses of the cell transistors, and developing a modified electric-field-relaxation scheme, an estimated cell leakage current of 88.7 fA/cell was achieved. We also developed a dual-word-voltage scheme to achieve stable operation of the cell during a read operation without affecting a write operation.