DocumentCode
1637206
Title
Modeling and estimation of failure probability due to parameter variations in nano-scale SRAMs for yield enhancement
Author
Mukhopadhyay, Saibal ; Mahmoodi-Meimand, Hamid ; Roy, Kaushik
Author_Institution
Dept. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
fYear
2004
Firstpage
64
Lastpage
67
Abstract
In this paper we have analyzed and modeled the failure probabilities (access time failure, read/write stability failure, and hold stability failure in the stand-by mode) of SRAM cells due to process parameter variations. A method to predict the yield of a memory chip designed with a cell is proposed based on the cell failure probability. The developed method can be used in the early stage of a design cycle to optimize the design for yield enhancement.
Keywords
CMOS integrated circuits; SRAM chips; integrated circuit reliability; integrated circuit yield; access time failure; failure probability; hold stability failure; nano-scale SRAMs; parameter variations; read/write stability failure; stand-by mode; yield enhancement; Circuit faults; Circuit stability; Fluctuations; MOSFETs; Probability; Random access memory; Semiconductor process modeling; Stability analysis; Threshold voltage; Yield estimation;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Circuits, 2004. Digest of Technical Papers. 2004 Symposium on
Print_ISBN
0-7803-8287-0
Type
conf
DOI
10.1109/VLSIC.2004.1346504
Filename
1346504
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