• DocumentCode
    1637756
  • Title

    Design and implementation of an algorithmic S2I switched-current multiplier

  • Author

    Manganaro, Gabriele ; De Gyvez, Jose Pineda

  • Author_Institution
    Dept. of Electr. Eng., Texas A&M Univ., College Station, TX, USA
  • Volume
    1
  • fYear
    1998
  • Firstpage
    37
  • Abstract
    The analysis, design and implementation of a S2I switched-current multiplier is presented. A thorough circuit analysis of the multiplier and its nonidealities is presented with a design procedure. It has been implemented using a 2 μm n-well CMOS technology. The following are brief highlights of the measurement results: (i) 0.425 millions of multiplication per second, (ii) 1.7% total harmonic distortion for a sinusoidal of 35 μA (50 Hz), (iii) 206 kHz of bandwidth, (iv) 50 dB of SNR and (v) 0.3 mW zero input power consumption for a ±3 V power supply. A complete set of detailed experimental results is provided in the paper
  • Keywords
    CMOS analogue integrated circuits; analogue multipliers; harmonic distortion; switched current circuits; -3 to 3 V; 0.3 mW; 2 micron; 206 kHz; 35 muA; SNR; algorithmic S2I switched-current multiplier; circuit analysis; n-well CMOS technology; nonidealities; total harmonic distortion; zero input power consumption; Algorithm design and analysis; CMOS technology; Circuit analysis; Clocks; Diodes; Distortion measurement; Power measurement; Switches; Switching circuits; Total harmonic distortion;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems, 1998. ISCAS '98. Proceedings of the 1998 IEEE International Symposium on
  • Conference_Location
    Monterey, CA
  • Print_ISBN
    0-7803-4455-3
  • Type

    conf

  • DOI
    10.1109/ISCAS.1998.704168
  • Filename
    704168
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1637756