Integration of logic synthesis and high-level synthesis into the DIADES design automation system

Author

Perkowski, M. ; Driscoll, M. ; Liu, J. ; Smith, D. ; Brown, J. ; Yang, L. ; Shamsapour, A. ; Helliwell, M. ; Falkowski, B. ; Wu, P. ; Ciesielski, M. ; Sarabi, A.

Author_Institution

Dept. of Electr. Eng., Portland State Univ., OR, USA

fYear

1989

Firstpage

748

Abstract

A description is presented of the high-level and logic synthesis stages in the digital design automation system DIADES. High level design, namely, data path synthesis, and control unit synthesis start from a parallel program graph, the form of description that includes both the control-flow and the data-flow graph. While the data path is allocated and scheduled, the control unit is designed to be composed of either microprogrammed units or finite-state machines. The latter are minimized in two dimensions (states and inputs), assigned and realized in logic. Several logic synthesis procedures, respective to various design styles and methodologies, can be used to design combinational parts of state machines, microprogrammed units, and data path logic

Keywords

combinatorial circuits; finite automata; logic CAD; DIADES; combinational parts; control unit design; control unit synthesis; control-flow graph; data path allocation; data path logic; data path scheduling; data path synthesis; data-flow graph; design methodologies; design styles; digital design automation system; finite-state machines; high level design; high-level synthesis; inputs; logic synthesis; logic synthesis procedures; microprogrammed units; parallel program graph; states; Automata; Automatic control; Concurrent computing; Contracts; Control system synthesis; Design automation; High level synthesis; Logic design; Microelectronics; Scholarships;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1989., IEEE International Symposium on

Conference_Location

Portland, OR

Type

conf

DOI

10.1109/ISCAS.1989.100459

Filename

100459