Sub-micron BiCMOS process design for manufacturing

Author

Lau, C.K. ; Lin, Chen-Hsi ; Packwood, Donald L.

Author_Institution

Hewlett-Packard Co., Palo Alto, CA, USA

fYear

1992

Firstpage

76

Lastpage

83

Abstract

A 0.5-μm BiCMOS process is used to illustrate the details in process design needed as a prerequisite for success in manufacturing. An existing CMOS process was used as the core for the BiCMOS process; CMOS design rules and performance were not altered by the addition of the bipolar processes. Issues related to bipolar integration, individual process modules, interactions between CMOS and bipolar, and manufacturability are discussed in detail. The specific performance targets for the bipolar devices are outlined. This process has been targeted to be used in building future high-performance ASIC products

Keywords

BiCMOS integrated circuits; application specific integrated circuits; integrated circuit manufacture; integrated circuit technology; 0.5 micron; ASIC products; BiCMOS process design; manufacturing; monolithic IC fabrication; submicron process; Application specific integrated circuits; BiCMOS integrated circuits; CMOS logic circuits; CMOS process; CMOS technology; Costs; Logic arrays; Logic devices; Manufacturing processes; Process design;

fLanguage

English

Publisher

ieee

Conference_Titel

Bipolar/BiCMOS Circuits and Technology Meeting, 1992., Proceedings of the 1992

Conference_Location

Minneapolis, MN

Print_ISBN

0-7803-0727-5

Type

conf

DOI

10.1109/BIPOL.1992.274079

Filename

274079