Design of area efficient and low power multipliers using multiplexer based full adder

This paper presents the modification of existing prominent multipliers like Wallace multiplier and Truncated Multiplier in order to improvise them in terms of power and area. In the existing Wallace multiplier architecture, the Carry Save Adder is replaced with Modified Carry Save Adder (MCSA)and further the full adder in the MCSA is implemented using Multiplexer. Similarly the regular full adder in the Truncated multiplier has been replaced with mux based full adder to achieve low area and power. Simulation of 8 × 8 Multiplier has been carried out with Modelsim 6.3c and Synthesis is carried out by Xilinx10.1. Results obtained show that the proposed modified multipliers offer low power and reduced area than the existing Multipliers.