GM_Learn: an iterative learning algorithm for CMOS gate matrix layout

An iterative CMOS gate matrix layout algorithm utilizing artificial intelligence (AI) learning techniques is presented. This GM_Learn algorithm features a rudimentary learning mechanism which improves the quality of a gate matrix layout through the repetitive application of a one-pass algorithm GM_Plan, developed by the authors. Two AI learning paradigms-rote learning and learning by parameter adjustment-are used in GM_Learn to modify the heuristic search parameters based on information of the previous solution. Preliminary results indicate that this novel algorithm is able to produce a high-quality gate matrix layout in only a few iterations. This method may be applicable to other combinatorial VLSI physical design problems where heuristic guided search is required