An improved negative level shifter for high speed and low power applications

An improved negative level shifter with high speed and low power consumption is presented. To reduce the switching delay and power consumption, a boost circuit is designed and additional charging current paths are introduced in the improved level shifter. The circuit has been designed in 130nm triple-well standard CMOS technology with a nominal power supply VDD of 1.5V and a negative voltage of -4.5V. Simulation results show that the switching delay and power consumption have been significantly reduced by roughly 78% and 51%, respectively, compared with the conventional negative level shifter.