A random delay design of processor against power analysis attacks

As an important implementation of Cryptographic algorithm, processor should be thought about the ability of resistant power attack. In this paper we show a processor architecture, which automatically detects the execution of the encryption algorithms, and interleaves the execution of cryptographic algorithm code with that of dummy instructions to reduce the correlations between the leakage and the inside operations, and thus make the statistic analysis infeasible. Experiment verifies the efficiency of the proposed method.