Research on modeling for the pattern library of interconnect parasitic capacitances in VLSI

At the present IC technologies, the accurately extraction of the interconnects parasitic parameters become more important. But for the time consuming, that computing the parameters of interconnects with field solver directly is impracticable. The common way is that establishing the pattern library according some typical Structures at the early design stage, then calculating the actual parameters after routing using these patterns. But for the pattern library establishment of interconnects parasitic parameters, how to determine the form of the pattern and how much sampling points should be selected, that are troublesome, which is related to both the time consuming and the accuracy of the model. In this paper, the authors provide a new modeling method, called error modification model method, and adopt a orthogonal sampling method, it can construct a parasitic parameter model in a relatively short time with high precision.