DocumentCode
1640762
Title
A high speed low power interface for inter-die communication
Author
Hua, Siliang ; Wang, Qi ; Yan, Hao ; Wang, Donghui ; Hou, Chaohuan
Author_Institution
Inst. of Acoust., Chinese Acad. of Sci., Beijing, China
fYear
2010
Firstpage
1916
Lastpage
1918
Abstract
In this paper a current mode logic (CML) transceiver with ±250mV output swing is proposed. The CML transceiver is designed according to inter-die communication model analysis. The model includes both bonding wire and transmission line based on electromagnetic analysis. The CML transceiver is implemented in 1.8V 0.18μm technology. Simulation results show that the transceiver can reach 2.4Gbps data rate and consumes only 27mW.
Keywords
current-mode logic; lead bonding; low-power electronics; system-in-package; transceivers; CML transceiver; bit rate 2.4 Gbit/s; bonding wire; current mode logic transceiver; electromagnetic analysis; high speed low power interface; inter-die communication model analysis; power 27 mW; size 0.18 mum; transmission line; voltage 1.8 V; Bonding; Driver circuits; Noise; Power transmission lines; Receivers; Transceivers; Wire;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State and Integrated Circuit Technology (ICSICT), 2010 10th IEEE International Conference on
Conference_Location
Shanghai
Print_ISBN
978-1-4244-5797-7
Type
conf
DOI
10.1109/ICSICT.2010.5667780
Filename
5667780
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