Multi-level approaches to low power 16-bit ALU design

Author

Ryu, Beom Seon ; Oh, Hyoung Sok ; Shim, Kie Hak ; Lee, Kie Young ; Cho, Tae Won

Author_Institution

Sch. of Electron. & Electr. Eng., Chungbuk Nat. Univ., South Korea

fYear

1999

fDate

6/21/1905 12:00:00 AM

Firstpage

158

Lastpage

161

Abstract

A low power 16-b ALU has been designed at the transistor level. The designed ALU performs 16 instructions and has a two-stage pipelined architecture. For low power consumption we propose a new ALU architecture which has efficient propagation (P) and generation (G) block schemes of ELM adder. The adder of the proposed ALU is disabled while the logic operation is performed and vice versa. Outputs of each P block are separated to the dual output bus to reduce switching capacitance during the ALU operation. The proposed ALU was simulated with O.6μm single-poly triple-metal CMOS process. As a result of post-layout simulations, addition time of the core is about 5ns with 3. 3 V supply voltage and the average power consumption of the core was 54 mW at 200 MHz

Keywords

CMOS logic circuits; adders; low-power electronics; multivalued logic circuits; pipeline processing; 0.6 micron; 16 bit; 200 MHz; 3.3 V; 5 ns; 54 mW; ALU architecture; ELM adder; addition time; average power consumption; dual output bus; low power ALU design; multi-level approaches; post-layout simulations; power consumption; single-poly triple-metal CMOS process; switching capacitance; two-stage pipelined architecture; Adders; Arithmetic; CMOS logic circuits; CMOS process; Capacitance; Clocks; Decoding; Energy consumption; Pins; Pipelines;

fLanguage

English

Publisher

ieee

Conference_Titel

ASICs, 1999. AP-ASIC '99. The First IEEE Asia Pacific Conference on

Conference_Location

Seoul

Print_ISBN

0-7803-5705-1

Type

conf

DOI

10.1109/APASIC.1999.824052

Filename

824052