Design and simulation of the vertical pnp transistor on SOI

Author

Luo, Jiexin ; Chen, Jing ; Zhou, Jianhua ; Wu, Qingqing ; Huang, Xiaolu ; Wang, Xi

Author_Institution

China State Key Lab. of Functional Mater. for Inf., Chinese Acad. of Sci., Shanghai, China

fYear

2010

Firstpage

1928

Lastpage

1930

Abstract

A vertical pnp BJTs on thin SOI is designed and characterized by using the mixed numerical two-dimensional process and device simulator (Sentaurus). The DC, frequency, and breakdown characteristics of the vertical pnp on SOI are simulated and analyzed. The peak of β is 85 at Vbe=-0.7. The maximum of the cutoff frequency f_τ for the pnp bipolar transistor on SOI attain 10.6 GHz, and the value of BVceo for the pnp bipolar transistor on SOI achieves -7.3V, respectively. The availability of performance pnp transistor should enable significantly improved bipolar circuit design.

Keywords

bipolar transistors; integrated circuit design; silicon-on-insulator; SOI; Sentaurus; bipolar circuit design; device simulator; mixed numerical two-dimensional process; pnp bipolar transistor; vertical pnp BJT; vertical pnp transistor; Bipolar transistors; Doping; Electric breakdown; Integrated circuits; Performance evaluation; Semiconductor process modeling; Transistors;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State and Integrated Circuit Technology (ICSICT), 2010 10th IEEE International Conference on

Conference_Location

Shanghai

Print_ISBN

978-1-4244-5797-7

Type

conf

DOI

10.1109/ICSICT.2010.5667792

Filename

5667792