Predictive modeling of capacitance and resistance in gate-all-around cylindrical nanowire MOSFETs for parasitic design optimization

This paper presents a predictive electrostatic capacitance and resistance compact model of multiple gate MOSFET with cylindrical conducting channels, taking into account parasitic effects, quantum confinement and quasi-ballistic effects. The model incorporates the dependence of channel length, gate height and width, gate-to-contact spacing, nanowire size, multiple channels, as well as 1-D ultra-narrow source/drain extension (SDE) doping profile. The proposed non-iterative electrostatic model is successfully verified, and can be used to predict nanowire-based circuit performance. Based on the analytical model, we can further examine which parasitic components are affecting the delay. Results revealed that C_side, C_of, R_sd, R_Q are dominant factors and should be treated as a major design concern. Among all the parameters, L_sd, T_g and N_dop are essentially important in parasitic design optimization. By selectively modifying these parameters, parasitic effect is evidently reduced.