A VPM (Virtual Pipelined Memory) architecture for a fast row-cycle DRAM

Author

Yoon, Chi-Weon ; Im, Yon-Kyun ; Han, Seon-Ho ; Hoi-Jun Yoo ; Jung, Tae-Sung

Author_Institution

Dept. of Electr. Eng., Korea Adv. Inst. of Sci. & Technol., Taejon, South Korea

fYear

1999

fDate

6/21/1905 12:00:00 AM

Firstpage

388

Lastpage

391

Abstract

We propose a Virtual Pipelined Memory (VPM) architecture for fast row-cycle by using a top-down design approach. A pipeline structure in the row path and integration of multiple SRAM buffers enable fast row-cycle. VPM shows higher performance than that of SDRAM by about 40% and that of VCM by about 20%. VPM maintains backward compatibility with a conventional SDRAM interface and consumes low power by adopting partial cell core activation

Keywords

CMOS memory circuits; DRAM chips; integrated circuit design; low-power electronics; parallel memories; pipeline processing; 64 Mbit; SDRAM interface; VPM architecture; backward compatibility; fast row-cycle DRAM; low power consumption; multiple SRAM buffer integration; partial cell core activation; pipeline structure; top-down design approach; virtual pipelined memory architecture; Bandwidth; Costs; Delay; Design methodology; Memory architecture; Performance analysis; Pipeline processing; Random access memory; SDRAM; System performance;

fLanguage

English

Publisher

ieee

Conference_Titel

ASICs, 1999. AP-ASIC '99. The First IEEE Asia Pacific Conference on

Conference_Location

Seoul

Print_ISBN

0-7803-5705-1

Type

conf

DOI

10.1109/APASIC.1999.824115

Filename

824115