• DocumentCode
    1643158
  • Title

    Faster Software Synthesis Using Actor Elimination Techniques for Polychronous Formalism

  • Author

    Jose, Bijoy A. ; Pribble, Jason ; Shukla, Sandeep K.

  • Author_Institution
    Bradley Dept. of Electr. & Comput. Eng., Virginia Polytech. Inst. & State Univ., Blacksburg, VA, USA
  • fYear
    2010
  • Firstpage
    147
  • Lastpage
    156
  • Abstract
    A visual polychronous formalism called Multi-Rate Instantaneous Channel Connected Data Flow (MRICDF)was developed in. In, a visual environment called EmCodeSyn was introduced which performs software synthesis from MRICDF models. The synthesis technique replaced clock calculus technique germane to previous polychronous approaches such as SIGNAL with a top down technique based on computing the Prime Implicates (PI) of set of Boolean constraints. This Prime Implicate based method first determines a totally ordered sequence of global synchronization points for all the computation, and then gradually determines if certain computations can synchronize less often. The sequence of global synchronization points are identified by subsequent changes in one of the signals in the system and it is called a master trigger. As opposed to bottom-up clock calculus this method can detect sequential non-implement ability faster. However, the PI computation time increases with the number of variables in the Boolean equations, which in turn increases with the size of the MRICDF network. For faster synthesis, we propose an actor elimination technique that enables reduction of the size of the PI computation problem while preserving the master trigger. Hence it provides a sound and complete abstraction technique for faster determination of sequential implement ability of an MRICDF based model.
  • Keywords
    Boolean functions; data flow analysis; program testing; Boolean constraint; Boolean equation; EmCodeSyn visual environment; MRICDF model; MRICDF network; PI computation; actor elimination; bottom-up clock calculus; global synchronization point; master trigger; multirate instantaneous channel connected data flow; prime implicate; software synthesis; visual polychronous formalism; Calculus; Clocks; Computational modeling; Equations; Generators; Mathematical model; Software; embedded software; multi-clock; multirate; polychrony; prime implicate; software synthesis; synchronous programming;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Application of Concurrency to System Design (ACSD), 2010 10th International Conference on
  • Conference_Location
    Braga
  • ISSN
    1550-4808
  • Print_ISBN
    978-1-4244-7266-6
  • Electronic_ISBN
    1550-4808
  • Type

    conf

  • DOI
    10.1109/ACSD.2010.31
  • Filename
    5552678