VLSI implementation of high speed two-dimensional state-space recursive filtering

The authors explore the parallelism in two-dimensional (2-D) state-space filter algorithms and propose some VLSI architectures for high-speed applications. First, the local state-space (LSS) realizations of 2-D IIR filters are reviewed. Then, two systolic array implementations, a direct form implementation, and a transformed implementation are obtained for realizing local speedup. They process one pixel during each clock time. To achieve very high speed, two global speed-up structures are used that exploit the inherent spatial concurrency. Based on the computational independence between the samples along the diagonal lines in a first-quadrant 2-D system, they work on multiple columns of images or multiple lines of images concurrently. The comparisons among the different architectures are also given. It is shown that the proposed architectures are attractive for high-speed, high-performance digital filtering