DocumentCode
1645515
Title
Integration of high-Q inductors in a latch-up resistant CMOS technology
Author
Frei, M.R. ; Belk, N.R. ; Dennis, D.C. ; Carroll, M.S. ; Lin, W. ; Pinto, M.R. ; Archer, V.D. ; Ivanov, T.G. ; Moinian, S. ; Ng, K.K. ; Chu, J.
Author_Institution
Bell Lab., Murray Hill, NJ, USA
fYear
1999
Firstpage
757
Lastpage
760
Abstract
Inductors fabricated using CMOS technologies based on epi/p/sup +/ substrates are severely degraded because of eddy current losses in the substrate. We propose and demonstrate a modified substrate structure, which addresses the conflicting goals of high inductor quality-factor and high latch-up immunity. Results include fabricated inductors with Q-factor as high as 16.
Keywords
CMOS integrated circuits; Q-factor; inductors; integrated circuit modelling; integrated circuit technology; substrates; Q-factor; eddy current losses; epi/p/sup +/ substrates; high latch-up immunity; high-Q inductors; inductor quality-factor; latch-up resistant CMOS technology; modified substrate structure; CMOS process; CMOS technology; Conductivity; Degradation; Doping profiles; Eddy currents; Impurities; Inductors; Q factor; Substrates;
fLanguage
English
Publisher
ieee
Conference_Titel
Electron Devices Meeting, 1999. IEDM '99. Technical Digest. International
Conference_Location
Washington, DC, USA
Print_ISBN
0-7803-5410-9
Type
conf
DOI
10.1109/IEDM.1999.824261
Filename
824261
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