A 360Mbin/s CABAC decoder for H.264/AVC level 5.1 applications

Author

Hong, Yu ; Liu, Peilin ; Zhang, Hang ; You, Zongyuan ; Zhou, Dajiang ; Goto, Satoshi

Author_Institution

Dept. of Electron. Eng., Shanghai Jiao Tong Univ., Shanghai, China

fYear

2009

Firstpage

71

Lastpage

74

Abstract

This paper presents a VLSI architecture of CABAC decoder for H.264/AVC level 5.1 applications. It adopts a symbol-prediction-based decision engine with extra-bypass decoding support, a four-stage bypass engine, along with dedicated arithmetic decoding modes to increase the throughput rate. It also reduces the context model access time significantly by applying context pre-fetch register set. The proposed design can decode an average of 1.08 bins per cycle, and can be operated at a maximum frequency of 333MHz using SMIC 0.13Â¿m technology. Therefore, it is able to provide a throughput of 360Mbins/s, and hence can meet the requirements of Level 5.1 in H.264/AVC standard.

Keywords

VLSI; adaptive codes; arithmetic codes; binary codes; video coding; CABAC decoder; H.264/AVC level 5.1; SMIC technology; VLSI architecture; arithmetic decoding modes; context pre-fetch register set; context-based adaptive binary arithmetic coding; decision engine; extra bypass decoding; four-stage bypass engine; size 0.13 mum; symbol prediction; Arithmetic; Automatic voltage control; Context modeling; Decoding; Delay; Engines; Entropy coding; Frequency; Throughput; Very large scale integration; CABAC; H.264; Level 5.1;

fLanguage

English

Publisher

ieee

Conference_Titel

SoC Design Conference (ISOCC), 2009 International

Conference_Location

Busan

Print_ISBN

978-1-4244-5034-3

Electronic_ISBN

978-1-4244-5035-0

Type

conf

DOI

10.1109/SOCDC.2009.5423878

Filename

5423878