Poly-Si TFTs with source overlap and drain offset structure

Author

Jang, H.K. ; Noh, S.J.

Author_Institution

Dept. of Phys., Korea Univ., Seoul, South Korea

Volume

1

fYear

1997

Firstpage

349

Abstract

Poly-Si TFTs have been investigated. The TFTs replacing conventional high resistive Poly-Si resistors were designed for applications to the load devices for mega-bit SRAMs. In order to achieve both a high memory cell stability and a low standby current maintaining a small cell area, bottom-gated Poly-Si TFTs with source overlap and drain offset structure were fabricated using a plasma hydrogenation process. The source overlap has a length of 0.0 to 0.2 μm and the drain offset, which is lightly doped, has a length of 0.1 to 0.4 μm. In experiment, 2,000 TFTs in parallel were used to measure small currents and the results obtained from dividing them by 2000 are the currents of a TFT. The on-current and the off-current have been measured and the optimum structure was determined when the on/off current ratio had the maximum value

Keywords

elemental semiconductors; semiconductor technology; silicon; thin film transistors; SRAM; Si; bottom-gated polysilicon TFT; drain offset; fabrication; load device; memory cell stability; on/off current ratio; plasma hydrogenation; source overlap; standby current; Electrical resistance measurement; Hydrogen; Physics; Plasma applications; Plasma devices; Plasma measurements; Plasma sources; Plasma stability; Resistors; Thin film transistors;

fLanguage

English

Publisher

ieee

Conference_Titel

Properties and Applications of Dielectric Materials, 1997., Proceedings of the 5th International Conference on

Conference_Location

Seoul

Print_ISBN

0-7803-2651-2

Type

conf

DOI

10.1109/ICPADM.1997.617602

Filename

617602