DocumentCode
1646556
Title
A Comma Detection and Word Alignment Circuit for High-Speed SerDes
Author
Yu Zhen ; Hu Qing-Sheng
Author_Institution
Inst. of RF-&OE-lCs, Southeast Univ., Nanjing, China
fYear
2011
Firstpage
1
Lastpage
4
Abstract
A comma detection and word alignment circuit is proposed for a 6.25-Gb/s SerDes. In order to achieve a high speed, a new architecture of combined parallel and pipelined is employed. Based on the proposed structure, a high speed comma detector is implemented using 0.18 μm CMOS technology. Post simulation result indicates that the circuit can operates up to 770MHz with a power consumption of 10.8 mW under 1.8V power supply.
Keywords
CMOS integrated circuits; detector circuits; integrated optoelectronics; optical fibre communication; parallel architectures; signal detection; CMOS technology; bit rate 6.25 Gbit/s; combined parallel architecture; comma detection circuit; fiber system; high-speed SerDes; power 10.8 mW; serial communication technology; signal detection; size 0.18 mum; speed comma detector; voltage 1.8 V; word alignment circuit; CMOS integrated circuits; Clocks; Decoding; Delay; Detectors; Registers; Synchronization;
fLanguage
English
Publisher
ieee
Conference_Titel
Wireless Communications, Networking and Mobile Computing (WiCOM), 2011 7th International Conference on
Conference_Location
Wuhan
ISSN
2161-9646
Print_ISBN
978-1-4244-6250-6
Type
conf
DOI
10.1109/wicom.2011.6040215
Filename
6040215
Link To Document