A scalable re-configurable processor

Several commercial and research projects have produced a variety of `computing surfaces´ based on FPGAs with some interconnection pattern. However, because the majority of these projects have constrained themselves to two-dimensional structures that can be fabricated on a single planar substrate, the interconnect patterns are fixed and severely constrain the ability of a problem to be mapped on to the prototyping system. This paper describes a simple development of the Achilles interprocessor switch. Achilles´ 3D stack of processors provides a flexible and scalable system-any number of stacks may be connected together in a small volume and a user may set up a connection pattern quite different from any envisaged by the hardware designer. Simulation of control systems where there are large numbers of objects such as traffic flows, network message traffic, etc, is CPU intensive and generally requires inordinately long runs on conventional sequential processors. So we have chosen Petri Net simulation for a feasibility study for Achilles as a reconfigurable processor. This showed that the architecture is particularly suitable for Petri Net simulations as hundreds of places in a net can be simultaneously active-reducing by orders of magnitude the time necessary for simulations