Trends in Test: Challenges and Techniques

Summary form only given. Ever increasing design sizes and the need for more sophisticated fault models at smaller process geometries require the use of compression technology to reduce the size of the ATPG pattern set. Otherwise those don´t fit on the automated test equipment. Compression is becoming the norm on the most advanced chips and is the enabling technology for true at speed testing of very large deep submicron designs. In this talk, the author reviews challenges and techniques for high quality at speed test at 90nm and below