• DocumentCode
    1648393
  • Title

    Polychronous Methodology For System Design: A True Concurrency Approach

  • Author

    Suhaib, Syed ; Mathaikutty, Deepak ; Shukla, Satyavati ; Talpin, Jean-Pierre

  • Author_Institution
    FERMAT Lab., Virginia Tech, Blacksburg, VA
  • fYear
    2006
  • Firstpage
    211
  • Lastpage
    214
  • Abstract
    As embedded systems have become pervasive and ubiquitous in contemporary technologies, their development requires highly reliable design approaches. One of these approaches is the so-called synchronous programming paradigm, where its mathematical basis provides the required formal concepts to satisfy correctness expectations. Among these synchronous programming concepts, the multi-clocked model of computation of polychrony stands out for its capability to give high-level and homogeneous descriptions of concurrent systems, where its concurrent parts may evolve asynchronously to each other and synchronize intermittently. In this paper, we propose a ´true concurrency´ semantic model of polychrony using pomsets. This formulation of polychrony closes the gap between synchrony and asynchrony by giving a uniform characterization of both synchronous and asynchronous observations by considering the causality and functional dependency structure of a pomset. The results in this paper also show that the existing tagged-signal model for polychrony uses an unnecessary artifact namely, tags, which complicate the semantic theory unduly
  • Keywords
    concurrency theory; embedded systems; program verification; set theory; synchronisation; systems analysis; embedded systems design; functional dependency structure; mathematical basis; multiclocked polychrony computation model; polychronous system design; pomsets; synchronous programming; true concurrency semantic model; Computational modeling; Computer networks; Concurrent computing; Conferences; Embedded system; Mathematical programming; Processor scheduling; Synchronization; System testing; USA Councils;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    High-Level Design Validation and Test Workshop, 2006. Eleventh Annual IEEE International
  • Conference_Location
    Monterey, CA
  • ISSN
    1552-6674
  • Print_ISBN
    1-4244-0679-X
  • Electronic_ISBN
    1552-6674
  • Type

    conf

  • DOI
    10.1109/HLDVT.2006.319993
  • Filename
    4110092