The need for a unified modeling language and VHDL-A

There is a strong desire for the control systems design community and the electronic design community to leverage off each other´s accomplishments in the area of modeling and simulation. In the past this has been impeded by the fact that they use different modeling languages and simulators, With the development of analog hardware description languages (AHDLs), which combine both discrete-time and continuous-time modeling and simulation capabilities, we are close to realizing this goal of a common modeling language. This paper investigates the modeling requirements associated with system design in an effort to illustrate capabilities desirable in a unified modeling language. It then provides an overview of the VHDL-A a candidate for unified modeling special session to place things into perspective. The combined package introduces VHDL-A (the language bring developed under IEEE DASC 1076.1) and discusses its suitability as a unified modeling language for control system design