Stability and yield-oriented ultra-low-power embedded 6T SRAM cell design optimization

This paper presents a methodology for the optimal design of CMOS 6T SRAM ultra-low-power (ULP) bitcells minimizing power consumption under strict stability constraints in all operating modes. An accurate analytical SRAM subthreshold model is developed for characterizing the cell behavior and optimizing its performance. The proposed design approach is demonstrated for an SRAM implemented in a 32nm CMOS UTBB-FDSOI technology. Stable operation in both read and write is obtained for the optimized cell at V_DD=0.4V. Moreover, in the optimization process the standby and active power were reduced up to 10x and 3x, respectively.