A Novel “hybrid” high-k/metal gate process for 28nm high performance CMOSFETs

Author

Lai, C.M. ; Lin, C.T. ; Cheng, L.W. ; Hsu, C.H. ; Tseng, J.T. ; Chiang, T.F. ; Chou, C.H. ; Chen, Y.W. ; Yu, C.H. ; Hsu, S.H. ; Chen, C.G. ; Lee, Z.C. ; Lin, J.F. ; Yang, C.L. ; Ma, G.H. ; Chien, S.C.

Author_Institution

ATD Exploratory Technol. Div., United Microelectron. Corp. (UMC), Tainan, Taiwan

fYear

2009

Firstpage

1

Lastpage

4

Abstract

A Â¿hybridÂ¿ high-k/metal gate (HK/MG) integration scheme is proposed in this paper to accomplish HP (high performance) 28 nm CMOSFETs by integrating gate-first/gate-last (GF/GL) techniques for N/PFET, respectively. For NFET, remarkable mobility (95% of n⁺poly/SiON@1MV/cm) and low V_TH (0.25 V) was achieved through optimized HfO₂ high-k, TiN metal and LaO_x capping layer processes. For PFET, an extra 30% performance improvement and a low V_TH (0.25 V) were achieved by GL process as a result of strain boost and VFB roll-off alleviation.

Keywords

MOSFET; high-k dielectric thin films; lanthanum compounds; titanium compounds; LaO_x; TiN; capping layer processes; gate-first-gate-last techniques; high performance CMOSFET; hybrid high-k-metal gate process; size 28 nm; CMOS technology; CMOSFETs; Capacitive sensors; Channel bank filters; Data mining; Hafnium oxide; High K dielectric materials; High-K gate dielectrics; Microelectronics; Tin;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting (IEDM), 2009 IEEE International

Conference_Location

Baltimore, MD

Print_ISBN

978-1-4244-5639-0

Electronic_ISBN

978-1-4244-5640-6

Type

conf

DOI

10.1109/IEDM.2009.5424256

Filename

5424256