Design optimization for single-event upset robustness using simultaneous dual-VDD and sizing techniques

An optimization algorithm for the design of combinational circuits that are robust to single-event upsets (SEUs) is described. A simple, highly accurate model for the SEU robustness of a logic gate is developed. This model - in posynomial form - is integrated with performance and power constraints into an optimization framework based on geometric programming for design space exploration. Simulation results for design optimization using simultaneous dual-V_DD and gate sizing techniques for the 70 nm process technology demonstrate the tradeoffs that can be achieved with this approach