DocumentCode
1650710
Title
Evaluation on efficient measurement setup for transient-induced latchup with bi-polar trigger
Author
Ker, Ming-Dou ; Hsu, Sheng-Fu
Author_Institution
Nanoelectron. & Gigascale Syst. Lab., Nat. Chiao Tung Univ., Hsinchu, Taiwan
fYear
2005
Firstpage
121
Lastpage
128
Keywords
CMOS integrated circuits; integrated circuit measurement; integrated circuit reliability; thyristors; transient response; 0.25 micron; CMOS IC reliability; SCR; TLU immunity; current-blocking diode; current-limiting resistance; electrical over-stress damage; ring oscillator test circuit; transient-induced latchup measurement; underdamped bi-polar trigger; CMOS technology; Circuit testing; Current measurement; Diodes; Electrical resistance measurement; Electromagnetic interference; Electrostatic discharge; Ring oscillators; Thyristors; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Reliability Physics Symposium, 2005. Proceedings. 43rd Annual. 2005 IEEE International
Print_ISBN
0-7803-8803-8
Type
conf
DOI
10.1109/RELPHY.2005.1493073
Filename
1493073
Link To Document