A 150 Mbit/s CMOS clock recovery PLL including a new improved phase detector and a fully integrated FLL

Author

Routama, J. ; Koli, Kimmo ; Halonen, Kari

Author_Institution

Electron. Circuit Design Lab., Helsinki Univ. of Technol., Espoo, Finland

Volume

1

fYear

1998

Firstpage

159

Abstract

This paper describes a 150 Mbit/s clock recovery PLL, which includes a new kind of phase detector. This phase detector has compensation logic for the minimum phase difference, which improves the transfer function significantly. The circuit has also a separate frequency locked loop (FLL) to ensure that the on-chip oscillator remains in the right locking range. The frequency loop is fully integrated and includes digital oscillator control. The circuit has been designed with a standard 0.5 μm CMOS process

Keywords

CMOS digital integrated circuits; compensation; data communication equipment; detector circuits; digital communication; digital phase locked loops; timing; 0.5 micron; 150 Mbit/s; CMOS clock recovery PLL; compensation logic; digital oscillator control; frequency locked loop; integrated FLL; minimum phase difference; onchip oscillator; phase detector; transfer function; CMOS logic circuits; CMOS process; Clocks; Detectors; Digital control; Frequency locked loops; Oscillators; Phase detection; Phase locked loops; Transfer functions;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1998. ISCAS '98. Proceedings of the 1998 IEEE International Symposium on

Conference_Location

Monterey, CA

Print_ISBN

0-7803-4455-3

Type

conf

DOI

10.1109/ISCAS.1998.704217

Filename

704217