Low noise clock synthesizer design using optimal bandwidth

Author

Lim, Kyoohyun ; Park, Chan-Hong ; Kim, Beomsup

Author_Institution

Dept. of Electr. Eng., Korea Adv. Inst. of Sci. & Technol., Taejon, South Korea

Volume

1

fYear

1998

Firstpage

163

Abstract

This paper presents a salient method to design a low noise clock synthesizer for high-speed data processing applications. The proposed design method optimizes the loop bandwidth by using a discrete-time analysis of a PLL and minimizes the clock synthesizer output jitter. Computer simulation is performed and simulation results strongly support the theoretical analysis. A 900 MHz clock synthesizer is experimentally designed and shows the minimum jitter at the optimum bandwidth obtained from the analysis

Keywords

CMOS digital integrated circuits; digital phase locked loops; integrated circuit noise; jitter; phase noise; timing circuits; 900 MHz; clock synthesizer output jitter; discrete-time analysis; high-speed data processing applications; jitter minimisation; loop bandwidth optimisation; low noise clock synthesizer design; optimal bandwidth; Application software; Bandwidth; Clocks; Computer simulation; Data processing; Design methodology; Design optimization; Jitter; Phase locked loops; Synthesizers;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1998. ISCAS '98. Proceedings of the 1998 IEEE International Symposium on

Conference_Location

Monterey, CA

Print_ISBN

0-7803-4455-3

Type

conf

DOI

10.1109/ISCAS.1998.704221

Filename

704221