DocumentCode
1651258
Title
RAG: An efficient reliability analysis of logic circuits on graphics processing units
Author
Li, Min ; Hsiao, Michael S.
Author_Institution
Bradley Dept. of Electr. & Comput. Eng., Virginia Tech, Blacksburg, VA, USA
fYear
2012
Firstpage
316
Lastpage
319
Abstract
In this paper, we present RAG, an efficient Reliability Analysis tool based on Graphics processing units (GPU). RAG is a fault injection based parallel stochastic simulator implemented on a state-of-the-art GPU. A two-stage simulation framework is proposed to exploit the high computation efficiency of GPUs. Experimental results demonstrate the accuracy and performance of RAG. An average speedup of 412× and 198× is achieved compared to two state-of-the-art CPU-based approaches for reliability analysis.
Keywords
circuit reliability; circuit simulation; graphics processing units; logic circuits; RAG; fault injection based parallel stochastic simulator; graphics processing units; logic circuit reliability analysis tool; two-stage simulation framework; Circuit faults; Computational modeling; Graphics processing unit; Integrated circuit modeling; Integrated circuit reliability; Logic gates;
fLanguage
English
Publisher
ieee
Conference_Titel
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2012
Conference_Location
Dresden
ISSN
1530-1591
Print_ISBN
978-1-4577-2145-8
Type
conf
DOI
10.1109/DATE.2012.6176487
Filename
6176487
Link To Document