DocumentCode
1651649
Title
A voltage scaling model for performance evaluation in digital CMOS circuits
Author
Von Arnim, Klaus ; Schruefer, Klaus ; Baumann, Thomas ; Hofmann, Karl ; Schulz, Thomas ; Pacha, Christian ; Berthold, Joerg
Author_Institution
Infineon Technol., Munich, Germany
fYear
2009
Firstpage
1
Lastpage
4
Abstract
We present an easy to use method to extrapolate digital circuit performance and power from nominal to worst-case operating conditions. It allows the circuit designer to explore the design space over a continuous rage of voltages and temperatures and for different process conditions. Voltage scaling is identified as a key challenge for the 22 nm technology node.
Keywords
CMOS digital integrated circuits; integrated circuit modelling; circuit designer; digital CMOS circuits; digital circuit performance evaluation; size 22 nm; voltage scaling model; CMOS digital integrated circuits; CMOS technology; Delay; Digital circuits; Dynamic voltage scaling; Semiconductor device modeling; Software libraries; Temperature distribution; Temperature sensors; Threshold voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Electron Devices Meeting (IEDM), 2009 IEEE International
Conference_Location
Baltimore, MD
Print_ISBN
978-1-4244-5639-0
Electronic_ISBN
978-1-4244-5640-6
Type
conf
DOI
10.1109/IEDM.2009.5424310
Filename
5424310
Link To Document