Performance analysis of ultra-scaled InAs HEMTs

Author

Kharche, Neerav ; Klimeck, Gerhard ; Kim, Dae-Hyun ; Del Alamo, Jeúss A. ; Luisier, Mathieu

Author_Institution

Birck Nanotechnol. Center, Purdue Univ., West Lafayette, IN, USA

fYear

2009

Firstpage

1

Lastpage

4

Abstract

The scaling behavior of ultra-scaled InAs HEMTs is investigated using a 2-dimensional real-space effective mass ballistic quantum transport simulator. The simulation methodology is first benchmarked against experimental I_d-V_gs data obtained from devices with gate lengths ranging from 30 to 50 nm, where a good quantitative match is obtained. It is then applied to optimize the logic performance of not-yet-fabricated 20 nm InAs HEMT. It is demonstrated that the best performance is achieved in thin InAs channel devices by reducing the insulator thickness to improve the gate control while increasing the gate work function to suppress the gate leakage.

Keywords

III-V semiconductors; ballistic transport; effective mass; high electron mobility transistors; indium compounds; semiconductor device models; work function; 2D real-space effective mass ballistic quantum transport simulator; InAs; gate length; gate work function; insulator thickness; logic performance; performance analysis; scaling property; size 20 nm; size 30 nm to 50 nm; thin InAs channel devices; two dimensional simulator; ultrascaled HEMT; Effective mass; HEMTs; Insulation; Logic devices; MODFETs; Nanotechnology; Performance analysis; Solid modeling; Thickness control; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting (IEDM), 2009 IEEE International

Conference_Location

Baltimore, MD

Print_ISBN

978-1-4244-5639-0

Electronic_ISBN

978-1-4244-5640-6

Type

conf

DOI

10.1109/IEDM.2009.5424315

Filename

5424315