Experimental demonstration of high mobility Ge NMOS

The highest electron mobility in Ge NMOS to-date, ~1.5 times the universal Si mobility, is demonstrated experimentally. Gate stack engineered with ozone-oxidation is integrated with low temperature S/D activation to fabricate Ge NMOS. Mechanisms responsible for poor Ge NMOS performance in the past are investigated with detailed gate dielectric stack characterizations and Hall mobility analyses for the first time. High S/D parasitic resistance, inversion charge loss due to trapping, and high interface trap density are identified as the mechanisms responsible for Ge NMOS performance degradation.